Regviz

NXP Semiconductors /MIMXRT1011 /DMAMUX /CHCFG[14]

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CHCFG[14]

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MIMXRT1011/DMAMUX/CHCFG[14]#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SOURCE0 (A_ON_0)A_ON 0 (TRIG_0)TRIG 0 (ENBL_0)ENBL

TRIG=TRIG_0, A_ON=A_ON_0, ENBL=ENBL_0

Description

Channel 0 Configuration Register

Fields

SOURCE

DMA Channel Source (Slot Number)
A_ON

DMA Channel Always Enable

0 (A_ON_0): DMA Channel Always ON function is disabled

1 (A_ON_1): DMA Channel Always ON function is enabled
TRIG

DMA Channel Trigger Enable

0 (TRIG_0): Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

1 (TRIG_1): Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
ENBL

DMA Mux Channel Enable

0 (ENBL_0): DMA Mux channel is disabled

1 (ENBL_1): DMA Mux channel is enabled

Links

()

Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data